The present invention relates to a computer system for conditionally executing instructions, to an execution unit for use in the computer system and to methods of executing instructions.
Computer systems are known where execution of an instruction is predicated on some value identified or addressed in the instruction. Computer systems are also known which act on so-called packed operands. That is each operand comprises a plurality of packed objects held in respective lanes of the operand. The degree of packing can vary and for 64 bit operands it is known to provide byte packing (eight objects per 64 bit operand), halfword packing (four objects per 64 bit operand) and word packing (two objects per 64 bit operand). With existing computer systems, when instructions defining such packed operands are predicated, the predication either causes the operation to be carried out on all of the operands or not to be carried out at all. Moreover, condition values are set depending on the results of the operation of an instruction.
There are computer systems where an instruction performs a particular test (e.g. compare for greater than) and sets a single bit for result true/false. Such instructions can be implemented on packed objects. For example, the packed compare instructions in the Intel MMX machine compare the corresponding data objects in the source and destination operands for equality or value greater than, respectively and generate a mask of ones or zeros which are written to the destination operand. Logical operations can use the mask to select elements. There is only a small group of such instructions, and these instructions always have the side effect of setting the true/false flags.
According to one aspect of the invention there is provided a method of executing instructions in a computer system on operands containing a plurality of packed objects in respective lanes of the operand wherein each instruction defines an operation and contains a condition setting indicator settable independently of the operation, the method comprising: determining the status of the condition setting indicator and, when the condition setting indicator is set; carrying out an operation specified in the instruction on each lane of the operand and generating a set of multibit condition codes depending on the results of carrying out the operation for each lane.
The arrangement according to the invention provides a number of advantages. In the first place, it provides a selectable ability to set condition codes alongside ordinary operations defined in an instruction. The condition setting indicator determines whether or not condition codes are set.
Moreover, the condition codes are multibit condition codes allowing for a number of different test conditions to be evaluated by subsequent instructions.
When the operand contains a maximum number N of packed objects, a condition code is individually generated for each lane whereby each set of condition codes contains N condition codes.
According to the following described embodiment, when operands contain less than the maximum number of packed objects (for example halfword or word packing), a condition code is generated for each lane of the operand and the value of that code is used to set two or more condition codes in the set of condition codes so that in the final set of condition codes there are N (the maximum number) of condition codes. This allows condition codes to be set on a lesser degree of packing and used by an operand with a greater degree of packing. In another embodiment, a condition code is set per lane of the packed operand so that the number of set condition codes depends on the degree of packing.
For a computer system which contains first and second execution channels, respective sets of condition codes can be generated for each execution channel.
The invention also contemplates accessing the condition codes in a subsequent instruction to determine on which lanes of the operand the operation specified in that subsequent instruction is to be carried out.
Another aspect of the invention provides a method of executing instructions in a computer system on operands containing a plurality of packed objects in respective lanes of the operand, the number of packed objects in the operand being less than the maximum possible number (N), the method comprising: carrying out an operation specified in the instruction on each lane of the operand and evaluating condition code values for each lane depending on the results of carrying out the operation for that lane; generating a set of condition codes containing a number of condition codes corresponding to the maximum possible number of packed objects in an operand by using the condition code value set for each lane of the operand to set two or more condition codes in the set of condition codes; and accessing each of said set of condition codes in a subsequent instruction which identifies an operand which is packed to a greater extent than the operand of the first instruction to determine on which lane of the operand for the subsequent instruction the operation specified in that subsequent instruction is to be carried out.
A further aspect of the invention provides a method of executing instructions in a computer system which comprises first and second execution channels, at least one instruction being executed on operands containing a plurality of packed objects in respective lanes of the operand, the method comprising: executing the instruction in the first execution channel by carrying out an operation specified in the instruction on each lane o the operand and generating a set of condition codes depending on the results of carrying out the operation for each lane; executing a subsequent instruction in the second execution channel including the step of accessing at least one of said set of condition codes to determine whether or not an operation specified in the subsequent instruction is to be carried out.
A further aspect of the invention provides an execution unit for use in a computer system for executing computer instructions, the execution unit comprising: first and second input stores for holding respective first and second operands on which an operation defined in the instruction is to be carried out, wherein each store defines a plurality of lanes each holding an object; a plurality of operators associated respectively with the lanes for carrying out an operation specified in the instruction on objects in corresponding lanes of the first and second source operands; a destination buffer for holding the results of the operation on a lane by lane basis; and a condition code generator for generating a set of condition codes depending on the results of carrying out the operation for each lane.
A further aspect of the invention provides a computer system comprising first and second execution channels, for carrying out respective operations; and a register file accessible by each of the first and second execution channels, said register file including a condition code register which holds a set of condition codes accessible by each of the first and second execution channels whereby a set of condition codes set by execution of an instruction in one of said execution channels is accessible by the other execution channel.
A further aspect of the invention provides a computer system comprising: a program memory ho ding a sequence of instructions for execution by the computer system, said instructions including a first instruction identifying at least one source operand containing a plurality of packed objects in respective lanes of the operand and having a condition setting field holding a condition set flag, and a second instruction which defines an operation to be executed and has a test field identifying a test code; at least one execution unit for executing said first and second instructions wherein pursuant to execution of said first instruction a set of condition codes are generated depending on the results of carrying out the operation for each lane of the operand if the condition set flag is set and wherein in execution of the second instruction the test code identified in the test field is compared with said condition codes to determine on which lanes of the operand the operation specified in the second instruction is to be carried out.
A further aspect of the invention provides a computer program product loadable into a computer system and comprising program code means including a sequence of instructions including: a first instruction identifying at least one source operand containing a plurality of packed objects in respective lanes of the operand and having a condition setting field holding a condition set flag, and a second instruction which defines an operation to be executed and has a test field identifying a test code, wherein when the computer program product is loaded into a computer system and the condition set flag inset, execution of the first instruction causes a set of condition codes to be generated depending on the results of carrying out the operation specified in the first instruction for each lane of the operand defined in the first instruction; and the second instruction conditionally implements the operation defined in the second instruction on individual lanes of the operand depending on the results of comparison of the test code identified in the second instruction with the generated set of condition codes.
For a better understanding of the present invention and to show how the same may be carried into effect, reference will now be made by way of example to the accompanying drawings.